Job Information
Capgemini Principal Products & Systems Engineer in Santa Clara, California
Life at Capgemini
Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:
Flexible work
Healthcare including dental, vision, mental health, and well-being programs
Financial well-being programs such as 401(k) and Employee Share Ownership Plan
Paid time off and paid holidays
Paid parental leave
Family building benefits like adoption assistance, surrogacy, and cryopreservation
Social well-being benefits like subsidized back-up child/elder care and tutoring
Mentoring, coaching and learning programs
Employee Resource Groups
Disaster Relief
About Capgemini Engineering
World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure & Transportation, Energy, Utilities & Chemicals, Life Sciences, Communications, Semiconductor & Electronics, Industrial & Consumer, Software & Internet.
Capgemini Engineering is an integral part of the Capgemini Group, a global leader in partnering with companies to transform and manage their business by harnessing the power of technology. The Group is guided every day by its purpose of unleashing human energy through technology for an inclusive and sustainable future. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, cloud and data, combined with its deep industry expertise and partner ecosystem. The Group reported 2023 global revenues of €22.5 billion.
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Disclaimer
Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.
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Director Custom ASIC Programs, RTL to GDSII - Solutions Architect
Summary
Person will be responsible for developing next generation SoCs for Hitech, consumer and automotive products and adjacencies. The role will require the candidate to understand and work on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. The person is also responsible for supervising physical design and verification aspects.
Responsibilities
Full chip design for multi million gates SoC
Digital design and development (RTL)
Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
Handle IP dependencies, planning and tracking of all front end design related tasks
Driving the project milestones across the design, verification and physical implementations
Lead interface to VCA partners for manufacturing and testing
Minimum Qualifications
Minimum 15 years of solid experience SoC design
Developing architecture and micro-architecture from specs
Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC
Understanding of Memory controller designs and Microprocessors is an added advantage
Understanding of Chip IO design and packaging is an added advantage
Familiarity with various bus protocols like AHB, AXI is highly desired
Ability to review top level test plans
Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC
Solid understanding of timing closure is a must
Needs to make effective and timely decisions, even with incomplete information.
Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas.
Provides direction, mentoring, and leadership to a small to medium sized groups.
Should possess strong communication and leadership skills to ensure effective communication with Program
SOC/ARM/RTL/SystemVerilog/Python/C/C
Job: Project Manager
Organization: ERD PPL US
Title: Principal Products & Systems Engineer
Location: CA-Santa Clara
Requisition ID: 075236
Other Locations: US-CA-San Diego, US-CA-San Jose, US-CA-San Francisco